TITLE: Reliability of Nano-Scaled Logic Gates Based on Binary Decision Diagrams

AUTHORS: Azam Beg and A. Beg

PUBLICATION/VENUE: 2014 International Conference on Modeling, Simulation and Visualization Methods (MSV'14), Jul 2014, pp. 1-5. [In press].


Binary decision diagrams (BDDs) have been useful for synthesis and verification of digital circuits. This paper, for the first time, looks into the reliability of a few logic gates implemented using BDDs. The gates were designed using an advanced CMOS technology node and subject to threshold-voltage variations. The results of the Monte Carlo Spice simulations show that BDD-based gates are significantly more reliable than their conventional CMOS counterparts.


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