AUTHORS: Azam Beg and A. Elchouemi
PUBLICATION/VENUE: 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2013, pp. 348-351.
The unrelenting scaling of CMOS devices has brought their dimensions down to few tens of nanometers. In such sizes, the reliability margins drop ominously and the leakage power dissipation increases significantly. This paper presents a non-conventional transistor-sizing method for improving reliability by increasing the static noise margin, while simultaneously reducing the power consumption. Simulations results have been used to compare the static noise margin, the power consumption, and the performance of classical CMOS gates with the proposed scheme in the 22 nm technology. The results show that modifying the channel lengths of transistors in inverters and other gates can improve the noise margin by nearly 40% over the conventional one, while reducing the power consumption by 47%. The robustness (measured here in terms of noise margin) of the classical and the new gates are also compared when their transistors are subject to threshold voltage variations.
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