TITLE: A Neural Model For Processor-Throughput Using Hardware Parameters And Software Dynamic Behavior

AUTHORS: Azam Beg, P.W.C. Chandana, A.K. Singh, and S.M.N.A. Senanayake

PUBLICATION/VENUE: 12th International Conference on Intelligent Systems Design and Applications (ISDA 2012), Nov 2012, pp. 821-825.


Design space exploration of a processor system, prior to its hardware implementation, usually involves cycle-accurate simulations. The simulations provide a good measure of performance but require long periods of time even when a small set of design variations are assessed. An alternative is to use empirically-developed models which are much faster than actual simulations. In this paper, we have proposed an NN model for processor performance (IPC) prediction. The model uses a larger set of input parameters (especially the software parameters) than the prior models. For dimension reduction, we found PCA to be a more useful technique than correlation and graphical analysis. For the purpose of training the NNs, we used the data from a large number of simulations of industry-standard SPEC CPU 2000 and SPEC CPU 2006 benchmark suites In order to collect the NN training data in a reasonable period of time, we utilized two well-known techniques, namely, benchmark-subsetting and SPs.


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