AUTHORS: V. Beiu, Azam Beg, W. Ibrahim, and F. Kharbash
PUBLICATION/VENUE: 2012 12th IEEE Conference on Nanotechnology (IEEE-NANO), Aug 2012, pp. 1-5.
This paper puts forward an enabling transistor sizing scheme targeting classical CMOS gates when implemented in advanced technologies. It relies on the well-known CMOS inverter for introducing the novel sizing concepts as well as for preliminary simulations verifying these concepts and comparing the resulting performances. These preliminary simulations support the claim that sizing has yet some potential as allowing to not only tradeoff delay versus power (which is well established and has been done over many years), but more interestingly: (i) to shape the static noise margins (SNMs); (ii) to adjust the threshold voltages; and (iii) to also confine threshold voltage variations. Such a sizing scheme can lead to highly reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which will operate correctly at the lowest possible voltages, hence potentially reaching new ultra-low voltage/power limits.
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