TITLE: Effect of Channel Lengthening And Threshold Voltage Variation On A Nanometric Gate's Delay And Power

AUTHORS: Azam Beg, A. Elchouemi, and R. Beg

PUBLICATION/VENUE: International Conference on Computer Design (CDES'12), Jul 2012, pp. 55-59.


Rapid scaling of CMOS devices in the recent years has not only increased the leakage power consumption but also increased the susceptibility of the circuits to device parameter variations. As a method for mitigating these effects, we have investigated the use of MOS transistors with longer-than-minimum channels. We performed Monte Carlo simulations to quantify the effects of threshold voltage variation and channel lengthening. With increased channel lengths, we were able to attain reduced susceptibility to the variations. Power reduction was also achieved but at the cost of performance. The longer-than-minimum channels technique could be useful for low power and mobile applications.


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