AUTHORS: W. Ibrahim, V. Beiu, and Azam Beg
PUBLICATION/VENUE: IEEE Transactions on Reliability, vol. 61, no. 3, Apr 2012, pp. 675-686.
Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, research on device-level redundancy has dragged for a few decades. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors, has led to a revival of interest for device-level redundancy schemes, especially during the last decade. In this paper we analyze transistor sizing as a method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. This approach has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides the very large scale integration (VLSI) designer with several transistor sizing options which allow to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the transistor sizing method proposed can improve the reliability of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than 10^5, 10, and 10^10 respectively, while the area is increased by at most 50%.
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