AUTHORS: W. Ibrahim, V. Beiu, and Azam Beg

PUBLICATION/VENUE: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 4, Apr 2012, pp. 509-521.

ABSTRACT:

Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PFGATE = const.), or 2) use very simple approaches to estimate the reliability of the elementary gates. In this paper, we introduce a gate reliability EDA tool (GREDA) that is able to estimate more accurately the reliability of CMOS gates by considering: 1) the gate’s topology; 2) the variable probability of failure of the individual devices (PFDEV); 3) the applied input vector; 4) the reliability of the input signals; and 5) the input voltage variations (which can be linked to the allowed noise margins). GREDA can be used to calculate PFGATE due to different types of faults and/or defects, and to estimate the effects of enhancing PFDEV on PFGATE. Simulation results show that GREDA can improve on the accuracy of reliability calculations at the gate level.

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