AUTHORS: V. Beiu, W. Ibrahim, Azam Beg, and M. Tache
PUBLICATION/VENUE: 4th HiPEAC Workshop on the Design for Reliability (DFR 2012), Jan 2012, pp. 1-4.
Scaling CMOS transistors has been used to achieve smaller, faster, and cheaper integrated circuits. However, with the aggressive scaling of the CMOS transistors into the nano-meter regime, the effect of threshold voltage (VTH) variations (besides other variations and noises) has started to significantly affect their reliability, as well as that of the gates’ they are forming. For mitigating against this trend, a sizing method which can significantly improve the reliability of CMOS gates has been proposed. The method can also reduce power or maintain speed while affecting area only marginally. For getting a better understanding, inverters designed using the new sizing method are compared in this paper with reliability enhanced inverters using well-known redundancy methods like triple modular redundancy and hammock networks. Simulation results show that, at the same reliability, the new sizing method can lead to designs outperforming those obtained by other methods on any of the design parameters (i.e., area, power or delay). These results support previous reports showing that space redundancy applied at the device-level leads to the most performant designs.
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