TITLE: On Pedagogy of Nanometric Circuit Reliability


PUBLICATION/VENUE: The Journal of Supercomputing, vol. 59, no. 2, Aug 2010, pp. 762-778.


Fast-shrinking dimensions of semiconductor devices are expected to reach sub-10 nm scale in a few years. Although smaller in size and lower in power consumption than today’ s CMOS devices, the nanoscaled devices are much less reliable due to manufacturing imperfections (hard errors), and noise and radiation-induced faults (soft errors). Consequently, in addition to timing, area, and power, the reliability has to become a new design criterion. This also means that the topic of reliability has to be incorporated into the circuit design curriculum. In this paper, we propose a course on circuit reliability. We also present in detail, an automated tool for calculation of reliability which could be incorporated into the course as a means for active learning.


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