TITLE: A Reduced-Dimension Processor Model


PUBLICATION/VENUE: Advances in Machine Learning and Data Analysis - Lecture Notes in Electrical Engineering, vol. 48, Jan 2010, pp. 43-56.


Architectural simulators used for microprocessor design study and optimization can require large amount of computational time and/or resources. In such cases, models can be a fast alternative to lengthy simulations, and can help reach a designer near-optimal system configuration. However, The non-linear characteristics of a processor system make the modeling task quite challenging. The models not only need to incorporate the micro-architectural parameters but also the dynamic behavior of programs. This paper presents a hybrid (hardware/software), non-linear model for processors. The model provides accurate predictions of processor throughput for a wide range of design space. We used different groups of code basic blocks to investigate their relationships to the execution efficiency of a superscalar processor. For this purpose, we utilized the frequencies of the blocks to represent runtime nature of 10 benchmark programs. We were able to reduce the number of hardware and software parameters by employing correlation coefficients and principal component analysis.


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