AUTHORS: P.W.C. Prasad, Azam Beg, and A.K. Singh
PUBLICATION/VENUE: IEEE Conference on Innovative Technologies in Intelligent Systems & Industrial Applications (CITISIA 2009), Jul 2009, pp. 165-170.
The minimization of logic gates is needed to simplify the hardware design area of programmable logic arrays (PLAs) and to speed up the circuits. The VLSI designers can use minimization methods to produce high speed, inexpensive and energy-efficient integrated circuits with increased complexity. Quine-McCluskey (Q-M) is an attractive algorithm for simplifying Boolean expressions because it can handle any number of variables. This paper describes a new model for the estimation of circuit complexity, based on Quine-McCluskey simplification method. The proposed method utilizes data derived from Monte-Carlo simulations for any Boolean function with different count of variables and product term complexities. The model allows design feasibility and performance analysis prior to the circuit realization.
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