TITLE: Relating Reliability to Circuit Topology

AUTHORS: Azam Beg and W. Ibrahim

PUBLICATION/VENUE: Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA'09), Jun 2009, pp. 1-4.


Reliability analysis of nano-scale circuits can be done using different techniques, one of them being Bayesian networks. Using this scheme, the relationship of circuit’s topology to reliability has been studied for several thousand randomly generated (combinational) 3 to 9 variable circuits; the circuits contained up to 40 gates in up to 10 tiers/levels. As anticipated, strong, positive correlations were found between gate counts and circuit’s probability of failure (PF), and between the level counts and circuit PF. However, the input counts and the circuit PFs were weakly correlated. These findings can be useful in creating reliability models for arbitrary circuits.


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