AUTHORS: Azam Beg and Yul Chu
PUBLICATION/VENUE: Journal of Circuits, Systems and Computers (JCSC), vol. 16, no. 5, Aug 2007, pp. 711-729. [Impact factor = 0.130].
Recent cache schemes, such as trace cache, (fixed-sized) block cache, and variable-sized block cache, have helped improve instruction fetch bandwidth beyond the conventional instruction caches. Trace- and block-caches function by capturing the dynamic sequence of instructions. For industry standard benchmarks (e.g., SPEC2000), performance comparison of various configurations of these caches using simulations can take days or even weeks. In this paper, we demonstrate that neural network models can be time-efficient alternatives to the simulations. The models are able to predict the multi-variate and non-linear behavior of trace- and block-caches, in terms of trace miss rate and average trace length. The models can be potentially used in compiler optimization or in pedagogical settings.
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