TITLE: Improved Instruction Fetching With A New Block-Based Cache Scheme

AUTHORS: Azam Beg and Yul Chu

PUBLICATION/VENUE: IEEE International Symposium on Signals, Circuits & Systems, Jul 2005, pp. 765-768.

ABSTRACT:

Instruction fetch speeds are improved by using cache schemes that are based on dynamic flow of program instructions. Variable-Sized Block Cache (VSBC) is a new instruction scheme that stores basic code blocks and their boundaries as traces. Current trace- or block-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. The studies done so far, in single- and multi-threaded environments, have shown improvements in trace miss rate. Other aspects of VSBC performance such as trace length and latency are being studied.

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