TITLE: Performance Analysis of Viterbi Decoder Using A DSP Technique

AUTHORS: S.K. Hasnain and Azam Beg

PUBLICATION/VENUE: 8th IEEE International Multitopic Conference (ITMIC'04), Dec 2004, pp. 201-207.


Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced.
Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel.
In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.


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